Take trainees through the complete digital chip implementation flow from synthesizable RTL to a signed-off, tape-out-ready GDSII database using industry-standard EDA tool
Who Can Apply?
Industry, CMOS & the ASIC flow.
Linux, EDA tools, Shell/Tcl & Git.
Professional communication & design reviews.
OHS & ESD practice.
Synthesisable RTL in Verilog/SystemVerilog, testbenches & simulation.
Logic synthesis, SDC constraints, QoR & static timing analysis.
Floorplan, power plan, placement, CTS, routing, extraction.
DRC, LVS, power, IR drop, signal integrity.
Low power, DFT & ATPG, formal, LEC, HLS.
Plan and execute a complete RTL-to-GDSII implementation, validate it against signoff criteria, document it, and present and defend it before reviewers.
