The course will give you an experience of chip design and an understanding of the part of chip design you are good at. By the end, you will have built a working IP yourself and carried it the whole way — RTL to tape-out-ready GDSII — on the same Cadence tools the industry runs
Who Can Apply?
Linux, shell and Tcl; digital logic and Verilog refresher; tool login.
Spec to synthesisable Verilog; self-checking testbench; waveform debug; SDC constraints; first netlist.
Floorplan and power plan; placement and congestion; clock tree synthesis; routing; post-route timing.
DRC rule decks and triage; LVS; antenna and density; parasitic extraction and SPEF.
STA, WNS/TNS and critical paths; ECO closure; IR drop and power integrity; GDSII stream-out.
Unseen spec: RTL, verification and synthesis, alone. Ends at gate review 1.
Route, verify, sign off, stream out; ten-minute panel review; gate review 2 issues the Lane Report.
