November 2026 Applications are open for the November 2026 VLSI design cohort

1-Week Digital Design

You'll be able to: Grasp digital-design and Verilog basics, run your first simulation, and leave with a working simulated RTL mini-block (e.g., a 4-bit ALU) plus a completion certificate.

Eligibility

Who Can Apply?

Any currently enrolled university student — 1st year to final year
No prior VLSI experience required
Degree in, or current enrolment in:
Electrical & Electronic (EEE)
Electronics & Communication (ECE)
Electronics & Telecommunication (ETE)
Computer Science & Engineering (CSE)
Other related disciplines
Assumed knowledge:
Basic digital logic — gates and flip-flops
Refreshed on day one, so a rusty memory is fine

Eligibility is advisory, not a gate. Enrolment is open — if you meet the knowledge bar for a course, you are welcome in it whatever year you are in.

Screening Process

Online Assessment & Written Assessment

Program Curriculum

Download brochure

Get the big picture of digital IC design.

Write simple combinational logic in Verilog.

Build a clocked FSM such as a traffic light.

Define your mini-project (e.g., a 4-bit ALU).

Compile and simulate your block.

Find and fix bugs using waveforms.

Implement your 4-bit ALU / FSM in Verilog.

Write a simple testbench and confirm behaviour.

Document and export your working project.