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ACI
ACI Semiconductor Limited
November 2026 Applications are open for the November 2026 VLSI design cohort

2-Week VLSI Explorer

You'll be able to: Sample both the digital and analog flows over two weeks and leave with a mini portfolio piece (a small RTL block and a laid-out cell), plus a completion certificate.

Eligibility

Who Can Apply?

  • Any currently enrolled university student — 1st year to final year
  • No prior VLSI experience, and no particular discipline required
  • Degree in, or current enrolment in:
    Electrical & Electronic (EEE)
    Electronics & Communication (ECE)
    Electronics & Telecommunication (ETE)
    Computer Science & Engineering (CSE)
    Applied Physics / Electronics
    Other related disciplines
  • Assumed knowledge:
    Nothing at all
    First-year students routinely finish this fortnight having started from zero
  • Eligibility is advisory, not a gate. Enrolment is open — if you meet the knowledge bar for a course, you are welcome in it whatever year you are in.

Screening Process

  • Online Assessment & Written Assessment

Program Curriculum

Download brochure

See the industry and its roles.

Map both design paths end-to-end.

Write simple Verilog logic.

Build a clocked FSM.

Simulate and debug your block.

Build a small working RTL block.

Understand the device and a basic stage.

Capture and simulate a simple cell.

Draw a basic cell layout.

Reach a DRC-clean cell.

Scope a small digital + analog deliverable.

Implement and verify the RTL piece.

Design and lay out the analog piece.

Package a portfolio piece and present it.