November 2026 Applications are open for the November 2026 VLSI design cohort

Analog IC Design & Schematic Entry

You'll be able to: Execute the analog design flow and build production-quality schematics in a managed design environment.

Eligibility

Who Can Apply?

Undergraduates in 3rd year and above
Graduates and practising analog engineers
Degree in, or current enrolment in:
Electrical & Electronic (EEE)
Electronics & Communication (ECE)
Electronics & Telecommunication (ETE)
Applied Physics / Electronics
Other related disciplines
Assumed knowledge:
MOS operation, biasing and single-stage amplifiers
Navigating Virtuoso
Running a basic simulation

Eligibility is advisory, not a gate. Enrolment is open — if you meet the knowledge bar for a course, you are welcome in it whatever year you are in.

Map the full analog design flow.

Set up a managed analog design environment.

Translate specifications into a design plan.

Apply a disciplined design-iterate loop.

Reason about PVT corners early.

Document and review an analog design.

Build a clean, review-ready schematic.

Manage hierarchy and bus connectivity.

Parameterize schematics for reuse.

Run checks and netlist for simulation.