You’ll be able to: Write synthesizable Verilog for combinational and sequential logic; trace a design from RTL all the way to GDSII.
Who Can Apply?
Understand what an HDL is and Verilog's role.
Build and connect modules hierarchically.
Use Verilog data types and the value system correctly.
Model combinational logic with continuous assignments.
Write procedural behaviour with correct sensitivity.
Model clocked sequential logic cleanly.
Design and code Mealy/Moore FSMs.
Factor designs with tasks and functions.
Build a basic testbench to exercise a design.
See how RTL becomes a gate-level netlist.
Understand floorplanning and placement.
Follow CTS and routing conceptually.
Reach a tapeout-ready database and GDSII.
