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ACI
ACI Semiconductor Limited
November 2026 Applications are open for the November 2026 VLSI design cohort

Functional Verification - SystemVerilog & SVA

You'll be able to: Build SystemVerilog testbenches, write SVA assertions, and apply coverage-driven verification.

Eligibility

Who Can Apply?

  • Undergraduates in 3rd year and above
  • Graduates and working engineers moving into verification
  • Degree in, or current enrolment in:
    Electrical & Electronic (EEE)
    Electronics & Communication (ECE)
    Electronics & Telecommunication (ETE)
    Computer Science & Engineering (CSE)
    Applied Physics / Electronics
    Other related disciplines
  • Assumed knowledge:
    Writing Verilog RTL
    Building a basic testbench
    Object-oriented ideas help, but classes are taught from scratch
  • Eligibility is advisory, not a gate. Enrolment is open — if you meet the knowledge bar for a course, you are welcome in it whatever year you are in.

Screening Process

  • Online Assessment & Written Assessment

Program Curriculum

Download brochure

See why SV extends Verilog for verification.

Use enums, structs and dynamic/associative arrays.

Encapsulate connectivity with interfaces.

Build testbench components with OOP.

Generate constrained-random stimulus.

Define covergroups and measure coverage.

Assemble a layered testbench.

Coordinate concurrent testbench threads.

Write immediate assertions to check behaviour.

Write concurrent SVA sequences.

Build properties with implication operators.

Use assertions for coverage and debug.