You’ll be able to: Explain the semiconductor industry and the full ASIC & custom-IC flow; tell digital and analog design paths apart; read a chip spec.
Who Can Apply?
See why SV extends Verilog for verification.
Use enums, structs and dynamic/associative arrays.
Encapsulate connectivity with interfaces.
Build testbench components with OOP.
Generate constrained-random stimulus.
Define covergroups and measure coverage.
Assemble a layered testbench.
Coordinate concurrent testbench threads.
Write immediate assertions to check behaviour.
Write concurrent SVA sequences.
Build properties with implication operators.
Use assertions for coverage and debug.
