October 2026 Applications are open for the October 2026 VLSI design cohort Apply Now

Physical Verification & Extraction (Assura)

You’ll be able to: Explain the semiconductor industry and the full ASIC & custom-IC flow; tell digital and analog design paths apart; read a chip spec.

Eligibility

Who Can Apply?

Final-year undergraduates
Graduates and layout engineers
Degree in, or current enrolment in:
Electrical & Electronic (EEE)
Electronics & Communication (ECE)
Electronics & Telecommunication (ETE)
Applied Physics / Electronics
Other related disciplines
Assumed knowledge:
A custom layout you built yourself
What DRC is, and why netlist-versus-layout matters

Eligibility is advisory, not a gate. Enrolment is open — if you meet the knowledge bar for a course, you are welcome in it whatever year you are in.

Screening Process

Step 1: Mini-Exam
Step 2: Online Interview

Program Curriculum

Download brochure

Understand DRC/LVS in signoff.

Run DRC and debug violations.

Run LVS and resolve mismatches.

Use cross-probing to fix LVS.

Handle antenna and advanced rule checks.

Understand RC parasitics and why they matter.

Extract parasitics from a verified layout.

Simulate with extracted parasitics.

Reach a tapeout-ready block.