November 2026 Applications are open for the November 2026 VLSI design cohort

Physical Verification & Tapeout Signoff

Eligibility

Who Can Apply?

Final-year undergraduates
Graduates and back-end engineers
Degree in, or current enrolment in:
Electrical & Electronic (EEE)
Electronics & Communication (ECE)
Electronics & Telecommunication (ETE)
Computer Science & Engineering (CSE)
Other related disciplines
Assumed knowledge:
A routed digital block
The ability to reason about timing
Linux and Tcl

Eligibility is advisory, not a gate. Enrolment is open — if you meet the knowledge bar for a course, you are welcome in it whatever year you are in.

See what stands between a routed design and a fab.

Run design-rule checks and debug violations.

Prove the layout matches the intended netlist.

Handle antenna, density and manufacturability rules.

Triage and fix violations efficiently on a real block.

Understand RC parasitics in the digital back-end.

Extract parasitics and generate SPEF.

Confirm timing still closes on the real design.

Produce a tapeout-ready GDSII.