November 2026 Applications are open for the November 2026 VLSI design cohort

RTL Simulation & Logic Synthesis

You'll be able to: Run professional simulation, regression and debug in Xcelium; synthesize RTL to gates with Genus and read timing/area reports.

Eligibility

Who Can Apply?

Undergraduates in 3rd year and above
Graduates and working RTL engineers
Degree in, or current enrolment in:
Electrical & Electronic (EEE)
Electronics & Communication (ECE)
Electronics & Telecommunication (ETE)
Computer Science & Engineering (CSE)
Other related disciplines
Assumed knowledge:
Synthesizable Verilog
Basic comfort at a Linux command line
No timing background needed — you read your first report here

Eligibility is advisory, not a gate. Enrolment is open — if you meet the knowledge bar for a course, you are welcome in it whatever year you are in.

Run the three-step simulation flow.

Debug with waveforms and probes.

Manage regressions and coverage collection.

Debug failures using assertions and logs.

Understand synthesis inputs and setup.

Elaborate RTL and apply generic optimization.

Drive synthesis with SDC constraints.

Map to the library and optimize for PPA.

Read and act on synthesis reports.

Produce a clean gate-level netlist for P&R.