November 2026 Applications are open for the November 2026 VLSI design cohort

Static Timing & DFT Signoff

You'll be able to: Run static timing signoff with Tempus; insert and verify DFT/scan with Modus; close timing and testability.

Eligibility

Who Can Apply?

Final-year undergraduates
Graduates and implementation engineers
Degree in, or current enrolment in:
Electrical & Electronic (EEE)
Electronics & Communication (ECE)
Electronics & Telecommunication (ETE)
Computer Science & Engineering (CSE)
Other related disciplines
Assumed knowledge:
Synthesis and SDC constraints
Reading a timing report
Linux and some Tcl scripting

Eligibility is advisory, not a gate. Enrolment is open — if you meet the knowledge bar for a course, you are welcome in it whatever year you are in.

Understand STA fundamentals.

Set up a signoff timing run.

Read violations and drive ECO fixes.

Account for SI in timing signoff.

Understand testability and scan design.

Insert and stitch scan chains.

Generate test patterns and measure coverage.

Close test coverage for signoff.