November 2026 Applications are open for the November 2026 VLSI design cohort

UVM Verification Methodology

You'll be able to: Build reusable UVM testbenches — agents, sequences, scoreboards — and run constrained-random, coverage-closed verification.

Eligibility

Who Can Apply?

Final-year undergraduates
Graduates and working verification engineers
Degree in, or current enrolment in:
Electrical & Electronic (EEE)
Electronics & Communication (ECE)
Electronics & Telecommunication (ETE)
Computer Science & Engineering (CSE)
Other related disciplines
Assumed knowledge:
SystemVerilog classes and constrained-random stimulus
Covergroups and functional coverage
A layered testbench you built yourself

Eligibility is advisory, not a gate. Enrolment is open — if you meet the knowledge bar for a course, you are welcome in it whatever year you are in.

Understand UVM's goals and class library.

Lay out agents, env and test hierarchy.

Build the core UVM components.

Model stimulus with sequences.

Use the config DB and factory overrides.

Connect components with TLM/analysis ports.

Check results and collect coverage.

Control run phases and end-of-test.

Package an agent into a reusable UVC.